1. Field of the Invention
This invention relates generally to the method and system of testing the electronic circuits including the integrated circuits (ICs). More particularly, this invention relates to an improved system configuration and method for simplifying and expediting the testing processes for electronic circuits including integrated circuits (ICs) by applying an improved algorithm by taking into account the defect probability as a key factor for generating the testing vector.
2. Description of the Prior Art
As the integrated circuits (ICs) and other form of electronic circuits become more complicate with higher level of integration and increasingly faster operational speed, the traditional techniques of the circuit testing configurations and methods are challenged by many technical difficulties. One of the major difficulties is the concept of “fault-coverage” in an attempt to more thoroughly and completely test the electronic circuits supported on either a semiconductor wafer or on other circuit support platforms applying various fabrication processes. Since the integrated circuit (IC) chip(s) is generally the most critical and expensive part of an electronic system, it is highly desirable to more thoroughly test the IC chip(s) to assure that functionalities as designed onto each IC chip can function properly. In order to achieve this goal, a high percentage of fault coverage is desirable. However, as the IC chips and electronic device becomes miniaturized to include large number of different transistors and accompanied circuits, high percentage fault coverage becomes an extreme heavy burden on the manufacturing and testing of the IC chips. As will be discussed further below, an IC chip designer is now required to design into the IC chips testing circuits for relieving this heavy burdens placed on testers of the IC chips to allow for more conveniently achieving a higher percentages of fault coverage in the testing processes and this is called DFT.
The development of the fault coverage concept in testing the electrical circuits started in an era before the IC fabrication and other similar techniques were developed. Prior to integrated circuit (IC) and other similar fabrication technologies, manual point-to-point crossed wiring with insulated copper wire and manual cabling are major tasks of the electric and electronic system manufacturing processing. In this type of process, the probability of any node being shorted or mis-wired to any other node is unpredictable or at the least very hard to characterize. However in that time, all the system complexity is very low in terms of test equipment capability. A one hundred percents (100%) fault coverage can be easily achieved. There are no practical needs to spend effort in reducing test vectors. However, in the meantime, the theory of fault coverage is formulated and firmly planted in the mind of the testing industries as an important index of merit in carrying out circuit tests.
Due to the rapid development of very large-scale integrated circuit (VLSI) and system on chip (S.O.C) technology, the extreme circuit complexity of state of art VLSI and S.O.C. has made testability becoming a major issue in the production process. The conventional pattern generation algorithm guided by fault coverage theory has come to a point that an astronomical number of test patterns are required to produce sufficient test coverage and that leads to the use of complex device to carry out very costly tests. In increasing numbers of cases, the test requirement becomes too complicate and not practical or economically not viable even by using those most advance test equipments.
One specific example is U.S. Pat. No. 6,385,750 issued to Kapur et al. They disclose a method and system for increase the fault coverage of test vectors for testing integrated circuits. The Kapur et al. provide a method and system for reducing the number of deterministic test vectors required for testing integrated circuits by inserting test points. A fault list having all the potential faults of an integrated circuit design is initialized and all the potential faults are marked as untestable. A set of test patterns, T, for testing several of the potential faults is generated. A fault simulation process is then performed on the integrated circuit design with the test patterns, T, to mark off untested faults. During fault simulation, fault propagation is monitored to determine the nets in the design to which faults were propagated. The nets at which fault propagation discontinues (e.g., de-sensitized) are also monitored. This information is collected over the set of test patterns, T. Based on the fault propagation information; test points are selectively inserted to maximize the fault coverage of the set of test patterns, T. In one embodiment, Kapur et al. also select nets to which most untested faults propagate for test point insertion and applying user-defined parameter to determine the selected number of test points. These steps are then repeated for another set of set patterns until the desired fault coverage is achieved. By adding test points, Kapur et al. intend to improve the fault coverage of the test patterns to reduce the test data volume. However, even with the benefits of reduced volume of testing data, as more testing points are added for the purpose of reducing the volume of test data, additional costs and time are required for carrying out the tests to include those inserted testing points.
To overcome this manufacturing bottle neck, a variety of testing techniques have been adapted such as BIST which needs additional circuitry to be incorporated into the device during early design stage thus costing not only silicon real state and design engineering time but also affecting device performance and capacity. Some other techniques such as IDDQ can only provide limited improvement but are not effective enough to remedy the problem significantly. All prior art have fault coverage as the goal and measurement of effectiveness, but in current production environment, different sets of test pattern with same fault coverage may have different numbers of malfunction device undetected in the same lot of devices.
Therefore, there is still a demand in the art of IC testing for a new technique and system configuration which can simplify the IC testing processes thus significantly reducing the requirements for expensive testing equipments, the long-hours of engineers' efforts for testing pattern generating and output signal simulation, the memory required for the storage of the testing input and output data, and the highly sophisticated control of exact timing in transmitting and collecting of these data.